The invention relates generally to electric signal and data processing and more particularly to a new and improved means for encoding a binary data word as a ternary code word and for decoding the ternary code word to recapture the binary data word for data transmission in a high speed network. The invention includes circuits for encoding and decoding the ternary code word and for maintaining DC balance in a series of transmitted ternary code words.
Binary (two-level) to ternary (three-level) data conversion has long been recognized as being beneficial for placement of data on an electromagnetic channel. Such a channel may be a storage medium such as a disk dive or magnetic tape or may be a transmission medium, such as an electric transmission line (twisted-pair). The three voltage levels (positive, negative, and zero, sometimes represented as the digits +, -, and 0) of ternary signals can provide a number of advantages over binary signals in data transmission and storage. One advantage is that ternary coding inherently carries more data per bit than binary data. For example, six binary bits can represent only 26 or 64 different values, whereas six ternary bits (or trits) can represent 3.sup.6 or 729 different values. This increased data carrying capacity can be effectively used to increase the speed of data transmission and the density of data storage.
The three levels of ternary data can also provide a way for eliminating the problem of an accumulated DC signal that can arise in binary data signals. A DC signal may arise in the transmission of a binary signal because the voltage on the signal line varies between a positive voltage level (such as +5) and 0 volts. During transmission of such a signal, the signal line will take on a overall positive charge, and this can increase sensitivity to signal distortion by noise or cross-talk interference. Ternary signals can eliminate this problem so long as the transmitted + and - voltage signals are in balance with each other. In order to effectively maintain DC balance, prior art ternary encoders include sometimes complex adder circuitry to keep a running total of the charge of transmitted ternary digits and have included an inverter circuit to invert selected transmitted ternary words when the accumulated DC voltage level diverges from zero. Some of these prior art encoders include additional information in the transmitted data to indicate when a word has been inverted.
Ternary signals can also be designed to incorporate a guaranteed number of voltage transitions on the media during a specified period of time. These guaranteed voltage transitions can be used to maintain data self-clocking and error checking. Some prior art ternary encoder circuits include a "repeat code" or other means to ensure periodic voltage transitions by preventing transmission of long strings of identical digits.
A number of binary-to-ternary encoders and decoders have been developed incorporating the above discussed principles, but thus far these circuits have been limited in the size of the binary word that is converted to a ternary code. Various methods and apparatus have been disclosed for translation of 2 binary bits to 1 ternary trit (2B1T), 3 binary bits to 2 ternary trits (3B2T), and 6 binary bits to 4 ternary trit (6B4T). Each of these translation methods claims specific advantages based on the translation used and each is designed for a particular application.
For example, U.S. Pat. No. 4,910,750, to Fisher, discloses a 3B2T code with a method for ensuring that no 2T code word is ever repeated during serial transmission. A claimed advantage of this invention is the facilitation of self-clocking by ensuring that a voltage transition occurs at least once during any two transmitted ternary words. The encoder uses a look-up table to accomplish the binary to ternary translation and a comparer with a memory to compare each to-be-transmitted word with the previously transmitted word and to substitute a "repeat" code whenever two words in sequence are identical. The use of the look-up table makes this invention impractical when applied to high speed network applications because the access time for look up table memories is too slow.
U.S. Pat. No. 4,779,073, to Iketani, discloses a 3B2T encoder with a look-up table similar to Fisher but including, in a second embodiment, an accumulator circuit and an inverter. The accumulator circuit determines the running "algebraic weight" of the transmitted ternary signals. The algebraic weight is defined as the sum of the ternary digits in the code word, where the two trit ternary code word "+0" would have an algebraic weight of plus one (+1) and the ternary code word "--" would have an algebraic weight of minus two (-2). The inverter is used to change the polarity of selected ternary words when the accumulated algebraic weight of transmitted words deviates from zero. The Iketani system uses a comparer to ensure that no 2T code word is ever repeated during serial transmission by replacing an even numbered pair of ternary symbols whenever two ternary code words in series are identical. DC balance is maintained through use of an inverter which inserts a "synchronous pattern" into the ternary data stream to let the decoder know when a code word has been inverted. One problem with the addition of the "synchronous pattern" into the ternary signal is that it reduces the overall speed of transmitted data and adds a data-dependent delay and circuit complexity to the Iketani system.
U.S. Pat. No. 4,387,366 to Chow discloses a 4B3T code converter with a PROM look-up table that stores inversion ternary code words along with non-inverted code words to maintain DC balance. A counter circuit adds up the algebraic weight of transmitted code words and selects the inverted ternary codes from the PROM to maintain DC balance when the balance deviates from zero. A claimed advantage of this invention is the facilitation of self-clocking by ensuring that a voltage transition occurs at least once during any two transmitted ternary words. As in Iketani, the look-up table and DC balance means are particularly unsuited for use in a high-speed network due to the slow access time of available memories that can serve as look-up tables.
Another encoder that uses a look-up table for binary to ternary translation is U.S. Pat. No. 4,092,595, to Weir, which discloses a 3B3T encoder.
U.S. Pat. No. 3,611,141, to Waters, discloses a 4B3T data transmission terminal that includes a disparity (or algebraic weight) checker and an inverter to maintain a zero DC balance. The binary to ternary translation uses combinatorial logic to translate from binary to ternary and provides a means to ensure that the maximum accumulated algebraic weight is four and that the longest possible string of identical ternary digits in a transmitted data stream is six. According to the system, no attempt is made in the translation to find a translation that uses a small number of logic gates. For this reason and because of the complexity of the disparity checking and inversion circuitry, the Waters system would be ineffective when applied to larger binary to ternary code conversions.
U.S. Pat. No. 4,244,052, to Hemsworth, provides a means for detecting misalignment of received words for a 6B4T translation system built according to the Waters system. Other systems that reference the Waters method for binary to ternary translation are U.S. Pat. No. 4,087,642 to Jessop (4B3T), and U.S. Pat. No. 3,902,117 to Sheppard (4B3T).
U.S. Pat. No. 4,631,428 to Grimes discloses a system for communicating data between binary chips using a 3B2T code converter that employs combinatorial logic. This system is not concerned with DC balance or other transmission issues and does not include means for addressing those problems. The system first translates the 3B code word to a 6B ternary control word which is used to control the 2T ternary drivers.
One specific application for binary to ternary translation that is not effectively addressed by the prior art systems is in high speed data transmission between computers in a network. On Sep. 28, 1993, the Fast Ethernet Alliance, a non-sanctioned technical group of the IEEE, proposed a new standard (the 4T+ Media Specification) for data transmission over four twisted pairs using a modification of the ethernet network protocol and using an 8B6T binary to ternary translation. The proposal was made to the IEEE 802.3 High-Speed Study Group. The 4T+ Media Specification proposes to achieve transmission speeds of 100 megabits per second using available ethernet transmission technology. This represents a 10 fold increase in speed over standard ethernet transmissions. As discussed above, prior art binary to ternary encoders are not well suited to perform the binary to ternary code conversion needed in this system.
What is needed is an 8B6T encoder and decoder and 8B to 6T code assignment that can utilize fast combinatorial logic, that efficiently preserves DC balance, that ensures frequent voltage transitions in a transmitted serial data stream and that is suited for high-speed processing and transmission in a computer network.